AMD Promises New Architecture for Zen 3, Adopts Intel Tick-Tock Model

The framing of the quote is a bit unclear, however. The Street : “Norrod observed that — unlike Zen 2, which was more of an evolution of the Zen microarchitecture that powers first-gen Epyc CPUs — Zen 3 will be based on a completely new architecture.” In the very next paragraph, however, Norrod is quoted as saying that Zen 3 will deliver performance gains “right in line with what you would expect from an entirely new architecture.”

AMD, according to Norrod, is confident in its ability to drive “significant IPC gains” each generation. TheStreet reports that AMD plans to rely on the tick-tock cadence that Intel popularized for a decade, in which a “tick” represents deploying an existing architecture on a new process, while a ‘tock’ refers to a new architecture on an existing process. Rome is a tick, despite the improvements from Zen to Zen 2, Milan will be a tock, and Genoa will be a tick again.

There are some oddities in this framing. The first part of the paraphrased quote implies that Zen 3 is a new architecture, while the second statement — which does include a direct quote — states that Zen 3 performance improvements are right in line with what you would expect from a new architecture. My take on this is that the word “architecture” is playing two roles here. There are major architectural shifts, like Bulldozer-Zen, and smaller updates that may improve on a CPU’s underlying performance, but don’t represent a fundamental change to how it operates. AMD’s tick-tock cadence also seems to be a bit different from Intel’s, in that it may include more room for actual evolution of the CPU architecture, even during “ticks,” given how much Rome improved on Naples while shifting to 7nm from 14nm.

Companies don’t actually deploy all-new architectures very often. Intel’s Ice Lake is an evolution of Skylake, which itself can be traced back to either Nehalem (if you date from Intel’s adoption of features like an integrated memory controller) or to Sandy Bridge (if you want to trace lineage using features like an opcache). Of course, in between these major releases, there are plenty of evolutionary changes that also get described as architectural updates. There are good reasons for companies to try and standardize on architectural features — it helps maintain good performance and backward compatibility over the long term.

I suspect that what Norrod is saying here is that AMD’s Zen 3 update will be big enough to qualify as a major architecture overhaul. It may include more significant changes to the underlying Zen design than AMD has made to-date. By the time Zen 3 debuts, AMD will have had Ryzen in-market for over three years, and that’s long enough to begin incorporating ideas the company had after Zen launched into Zen 3’s core design. I seriously doubt the company would jettison the Zen architecture altogether, but it’s possible that there are significant improvements planned.

As for rumors of improved clock on 7nm+, TSMC hasn’t given any guidance pointing to dramatic improvements from EUV, so we’ll just see where that takes us. This is the first time the foundry has ever built big-core x86 CPUs in these TDPs, so we can’t even look to historical performance for a sense of whether AMD will bring clock speeds up.

Each generation of Zen has delivered significant IPC improvements and AMD has been hitting its IPC improvements. Norrod isn’t giving details, but he seems to be laying the stage for further uplift in 2020 on the 7nm+ node. After a year as big as 2019 has been for AMD my expectations for further improvements in 2020 were modest, but AMD seems to think it can continue delivering double-digit gains year-on-year. We haven’t said much about Intel in all this — Ice Lake delivered significant IPC improvements over Skylake (~1.18x), but traded off frequency against its older cousin. Intel’s 10nm is currently only shipping in mobile, so we can’t comment on how future desktop products may evolve.

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